Low noise output buffer capable of operating at high speeds

ABSTRACT

Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

PRIORITY CLAIM

The present application claims priority from Indian Patent ApplicationNo. 2615/Del/2004 filed Dec. 31, 2004, the disclosure of which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a low noise output buffer capable ofoperating at high speeds.

2. Description of Related Art

Noise in the power supplies is one of the major concerns while designinghigh-speed digital and analog I/O circuits. One of the major sources ofsupply noise is the switching of output drivers. The faster the I/O,more current it requires and that implies higher noise. This may causefunctional failures on chip. So, the check on the noise has become amain concern while designing high-speed output drivers.

Further, as CMOS devices are scaled down into the deep sub-micronregion, the operating frequency of an output driver is increased (e.g.,to frequencies over 50 MHz), which is reflected in terms of a reductionin rise/fall times and pulse widths. High switching speed leads to afast rate of change of current (di/dt). A Simultaneous Switching Noise(SSN) is created when many output drivers connected to a single supplyswitch simultaneously in the presence of a chip-package interface powerdistribution parasitic. This SSN must be limited to within the maximumallowable noise level in order to guarantee normal functioning of thebuffers and the devices connected to the same supply. Therefore, powerand ground noises have to be controlled for reliable operation of thelogic devices. Some of the encountered problems with false operationsdue to SSN are false triggering, double clocking and/or missing clockedpulses. A typical chip-package interface is shown in FIG. 1.

Supply and ground bounce due to SSN can be expressed as:Vbounce=n*L*di/dtWhere n is the number of buffers switching together, L is the cumulativeinductance of the trace, bonding wire and metal rail interconnects anddi/dt is the rate of change of current of an output driver flowingthrough the supply and ground pad. As the parameters n and L (due to thelimitation from packaging) are not in the designers hands, the onlyquantity that can be controlled is the current slew rate for controllingsupply/ground noise.

Supply noise can be suppressed by reducing the rate of change ofcharging and discharging current at the load. The rate of change ofcharging/discharging can be monitored by controlling the signalsconnected to gate of output driver (i.e., GN and GP in FIG. 3) and/orusing appropriate sized output driver transistors. The sizes of outputdriver transistors, however, are fixed due to the output impedancematching requirement with that of the characteristic impedance of thetransmission line or output drive specification for driving the TTL/CMOSload.

FIG. 3 shows a block diagram of conventional compensated CMOS outputbuffer. It comprises of tri-state logic 30, active slew rate control 31,compensation cell 32, output driver transistors 33 and 34 connected tothe output pad of the integrated circuit and a load capacitor 35. Thecircuit shows the output buffer being compensated for slew rate at therising edge only.

Generally, a pre-driver is used for controlling the slope of the signalconnected to the gate of output driver by which the slew on the risingedge can be controlled while the slew on the falling edge can becontrolled by sizing of output driver. But in case of high speedbuffers, the output current is quite high due to the low outputimpedance of the driver when the PAD is at VOH and VOL levels and fallsabruptly when input transits. When the input makes a transition fromlogic low to high, current at the load starts rising first and thenstarts falling gradually as the output driver PMOS goes in linearregion. Also, voltage at the PAD starts rising and reaches the requiredVOH value but there is an abrupt fall in the current due to change inlogic at the input (from high to low) of the buffer as shown in waveform2 of FIG. 4. This steep fall of current from high value to zero whenPMOS goes off at the falling edge of the current creates noise due tohigh value of slew rate when many output buffers switch together.

Thus, a circuit providing slew rate limitation at the falling edge isrequired.

There is accordingly a need to control the slew rate at the falling edgeof current of the CMOS output driver.

There is further a need to provide a low noise output buffer capable ofoperating at high speeds.

SUMMARY OF THE INVENTION

An embodiment of the proposed invention allows a smooth currenttransition as seen by the supply so that di/dt of the current flowingthrough supply is not too large. An additional current bypass circuit isadded to the conventional output buffer circuit that turns on as soon aseither of output drive transistors turns off abruptly due to a change ininput logic. Thus, the additional current in bypass circuit adds to thecurrent flowing through output driver to make it smooth as seen bysupply pad.

A embodiment of the instant invention provides a low noise output buffercapable of operating at high speeds comprising a ground/supply, a maincircuit wherein a slew rate limiting means is connected to saidground/supply and said main circuit for the falling edge of the outputswitching signal.

Said slew rate limiting means include microelectronic transistorsconnected to said main circuit depending upon the requirement of themain circuit.

Said slew rate limiting means include MOS transistors connected to saidmain circuit depending upon the requirement of the main circuit.

Said slew rate limiting means include CMOS transistors connected to saidmain circuit depending upon the requirement of the main circuit.

Said main circuit includes an output buffer.

A method of controlling noise in output buffers capable of operating athigh speeds comprising the steps of sourcing/sinking the current in theslew rate limiting means at the falling edge of the output switchingsignal.

In accordance with another embodiment, an output buffer comprises a CMOSoutput driver having first complementary inputs and a first output, apre-driver circuit having second complementary inputs and firstcomplementary outputs, the first complementary outputs being coupled tothe first complementary inputs, and a falling edge slew rate controlcircuit coupled to the second complementary inputs.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the method and apparatus of the presentinvention may be acquired by reference to the following DetailedDescription when taken in conjunction with the accompanying Drawingswherein:

FIG. 1 shows a typical chip package interface parasitics;

FIG. 2 is an Output Driver final stage equivalent circuit;

FIG. 3 is a conventional compensated CMOS Output Driver;

FIG. 4 shows a waveform in accordance with invention;

FIG. 5 shows a block diagram of an embodiment of the instant invention;

FIG. 6 is a circuit diagram for an embodiment of the instant invention;

FIG. 7 shows simulation results for vdd/gnd at 55 MHz at 80 pf load.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 4 shows the waveforms in accordance with invention. The firstwaveform corresponds to an input signal. The proposed circuit senses thechange in the logic level of the input signal (waveform 1 of FIG. 4) andtriggers on when the output driver transistor goes off. The secondwaveform corresponds to the current profile of an output driver whilecharging or discharging the load. The third waveform corresponds to thecurrent profile of the additional circuit for limiting slew rate at thefalling edge of the input signal. The fourth and fifth waveforms referto the smooth curves obtained at source/sink due to the additionalcircuit.

FIG. 5 shows the block diagram of the instant invention. The circuitconsists of a main circuit 50, additional circuit 51 for providing slewrate limitation at the falling edge and a supply 52/ground 53. The maincircuit 50 is basically a circuit for which the slew rate at the fallingedge is to be controlled. Both the main circuit 50 and the additionalcircuit are connected to the supply 52/ground 53 for sourcing or sinkingcurrent.

When the input signal A (waveform 1 of FIG. 4) is applied, the currentin the main circuit 50 starts rising and follows the trajectory as shownin waveform 2 of FIG. 4. It can be seen from the waveform that the slewrate is controlled at the rising edge using the compensation cell. Assoon as the input signal (waveform 1 of FIG. 4) transits from high tolow, an abrupt fall off of current occurs (waveform 2 of FIG. 4). Inorder to avoid this abrupt current fall, the additional circuit 51 comesinto play with a current profile as shown in waveform 3 of FIG. 4. Theadditional circuit provides an alternate path to the supply current andtherefore removes the possibility of abrupt transition of current (see,dotted lines in waveforms 4 and 5 of FIG. 4). This is furtherillustrated using an embodiment.

Referring to FIG. 6 (in combination with FIG. 3), the NIN and PINsignals are delayed version of the input signal A. When EN is logicHIGH, the output driver is tri-stated, signal PIN goes low (GP goeshigh) and NIN goes high (GN goes low). The nodes GN and GP arecontrolled for slew control using pre-driver transistors 61 and 62. Whenoutput driver PMOS 63 is ON (Input high), the voltage at node GP iscontrolled (slowly decreased) to control the slew rate at the risingedge. In the same way, signal at node GN is controlled when outputdriver NMOS 64 is ON. So, when input changes from high to low (i.e. nodeGP goes from low to high), output driver PMOS 63 goes off and being veryhigh drive, current falls abruptly from high value to zero (see,waveform 2 of FIG. 4). To avoid the abrupt change in the current fromsupply, a PMOS 66 is turned on using signal NIN that goes low (when GPgoes high) while the falling of the current from supply is controlled bycharging the capacitor 68. The same process is followed when input goeslow and the additional circuit NMOS 67 turns on to discharge thecapacitor 68. The inputs of the circuit 66/67 are accordinglycross-coupled connected to the NIN/PIN inputs.

The sizes of the transistors 66 and 67 and capacitor 68 are calculatedusing simple analysis. In the present case this circuit is designed tooperate at 55 Mhz at 80 pf capacitive load with the specifications onthe output driver as a maximum slew rate of 20 mA/ns and outputimpedance of 50 ohms. Specified values of the VOH and VOL are 0.8*Vddand 0.2*Vdd, respectively. The peak current of the transistors 66 and 67can be set to the same value of the output current when the input makesa transition (i.e. when the voltage at PAD crosses VOH for 66 and VOLfor 67). The value of the capacitor 68 can be set for the desiredfalling slew rate of the supply current.

SIMULATION RESULTS: FIG. 7 shows the three graphs plotted to show thenoise reduction using the instant invention over the prior art.

The first diagram shows the pulse input and output of the output driver.

The second diagram shows the noise in the 2.1V supply with and withoutusing additional circuit. It can be seen that there is not much of adifference in the noise at the rising edge but the noise at falling edgeis drastically reduced.

The third diagram shows the ground noise with and without additionalcircuit. The difference in the ground noise at the falling edge of thecurrent can be seen. The results have also been tabulated in Table 1.TABLE 1 Supply/ground noise comparison Bounce/drop(max) Bounce/drop(max)with add. ckt without add. ckt Vdd bounce/drop 0.55 V 0.81 V Gndbounce/drop 0.52 V 0.84 V

When the additional circuit of the proposed invention is used, at lowerfrequencies output driver current has enough time to come down to lowvalue. This creates a small spike of current due to additional circuitwhich adds a bounce to supply, but it is ensured that the bounce createdis not going to effect the normal operation as the level of bouncecreated is lower than the bounce created by the rising edge slew of thecurrent.

Looking at the results, it can be concluded that the above-mentionedinvention for controlling slew rate is very effective if the outputdriver is used at a predetermined frequency. This circuit has beendesigned for a worst case where the effect of noise on the driver ismaximum. But the proposed circuit can be compensated using the digitalcodes from the compensation cell to make it even more effective at theslow corners. This is a novel method/apparatus to increase operatingfrequency without increase in supply/ground bounce.

Although preferred embodiments of the method and apparatus of thepresent invention have been illustrated in the accompanying Drawings anddescribed in the foregoing Detailed Description, it will be understoodthat the invention is not limited to the embodiments disclosed, but iscapable of numerous rearrangements, modifications and substitutionswithout departing from the spirit of the invention as set forth anddefined by the following claims.

1. A low noise output buffer capable of operating at high speedscomprising: a ground/supply, a main circuit for generating outputsignals connected to said ground/supply, and a slew rate limiting meansconnected to said ground/supply and said main circuit for controllingslew rate of the falling edge of the output switching signal.
 2. The lownoise output buffer as claimed in claim 1 wherein said slew ratelimiting means comprises transistors whose control terminals areconnected to inputs of said main circuit.
 3. The low noise output bufferas claimed in claim 1 wherein said transistors are MOS transistors. 4.The low noise output buffer as claimed in claim 1 wherein saidtransistors are CMOS transistors.
 5. The low noise output buffer asclaimed in claim 1 wherein said main circuit includes an output buffer.6. A method of controlling noise in output buffers comprising the stepsof sourcing/sinking the current selectively at the falling edge of anoutput switching signal in response to changes in an input signal.
 7. Anoutput buffer, comprising: a CMOS output driver having firstcomplementary inputs and a first output; a pre-driver circuit havingsecond complementary inputs and first complementary outputs, the firstcomplementary outputs being coupled to the first complementary inputs;and a falling edge slew rate control circuit coupled to the secondcomplementary inputs.
 8. The output buffer of claim 7 wherein thepre-driver circuit includes a rising edge slew rate control circuit. 9.The output buffer of claim 7 wherein the falling edge slew rate controlcircuit comprises a CMOS transistor circuit having third complementaryinputs, wherein the third complementary inputs are cross-coupledconnected to the second complementary inputs.
 10. The output buffer ofclaim 9 wherein the falling edge slew rate control circuit furthercomprises a dummy capacitance coupled to a connection node betweentransistors of the CMOS transistor circuit.
 11. The output buffer ofclaim 10 wherein a value of the dummy capacitance is selected to set adesired falling edge slew rate.
 12. The output buffer of claim 7 whereinthe falling edge slew rate control circuit comprises a CMOS transistorcircuit having third complementary inputs and a second output, whereinthe third complementary inputs are cross-coupled connected to the secondcomplementary inputs and the second output is not coupled to the firstoutput.
 13. The output buffer of claim 12 wherein the falling edge slewrate control circuit further comprises a dummy capacitance coupled tothe second output.
 14. The output buffer of claim 12 wherein the firstoutput is coupled to a pad of an integrated circuit.
 15. The outputbuffer of claim 14 further comprising an output capacitance coupled tothe first output.
 16. The output buffer of claim 7 wherein the CMOSoutput driver, the pre-driver circuit and the falling edge slew ratecontrol circuit are all coupled between a common supply voltage and acommon ground voltage.
 17. The output buffer of claim 16 wherein thefalling edge slew rate control circuit comprises a CMOS transistorcircuit having third complementary inputs and a second output, whereinthe third complementary inputs are cross-coupled connected to the secondcomplementary inputs and the second output is not coupled to the firstoutput.
 18. The output buffer of claim 17 wherein the first output iscoupled to a pad of an integrated circuit.